The present invention relates to a semiconductor device, and more particularly to a semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells having a reduced ON-resistance between source and drain, a reduced threshold voltage and an increased source-drain withstand voltage as well as a method of optimization of two-dimensional arrays of double diffused MOS field effect transistor cells for obtaining possible reductions in channel resistance and threshold voltage of the double diffused MOS field effect transistor cells.
FIGS. 1A through 1G are fragmentary cross sectional elevation views illustrative of a method of forming a double diffused MOS field effect transistor over a semiconductor substrate.
With reference to FIG. 1A, a gate oxide film 2 having a thickness of 20-200 nanometers is formed on an n-type semiconductor substrate
With reference to FIG. 1B, a gate polysilicon layer 3 is deposited on the gate oxide film 2 by a chemical vapor deposition method so that the gate polysilicon layer 3 has a thickness of 300-600 nanometers. The gate polysilicon layer 3 is then doped with phosphorus to reduce a resistivity thereof.
With reference to FIG. 1C, the phosphorus-doped gate polysilicon layer 3 and the gate oxide film 2 are patterned by a photolithography technique, thereby to form a gate electrode 3 so that a predetermined region of the n-type semiconductor substrate 1 is shown.
With reference to FIG. 1D, an p-type impurity is ion-implanted into the predetermined region of the n-type semiconductor substrate 1 so that a p-type base region 4 is selectively formed in an upper region of the n-type semiconductor substrate 1.
With reference to FIG. 1E, an n-type impurity is selectively ion-implanted into selected regions of the p-type base region 4 so that n+-type source regions 5 are selectively formed in selected upper regions of the p-type base region 4.
With reference to FIG. 1F, an inter-layer insulator 6 having a thickness of 300-1500 nanometers is entirely formed over the gate electrode 3, the n+-type source regions 5 and the p-type base region 4. A contact hole is formed in the inter-layer insulator 6 so that the contact hole is positioned over inside half of each of the n+-type source regions 5 and the p-type base region 4.
With reference to FIG. 1G, an aluminum electrode 7 having a thickness of 1-3 micrometers is entirely deposited over the inter-layer insulator 6, the over inside half of each of the n+-type source regions 5 and the p-type base region 4, so that the aluminum electrode layer 7 is made into contact with the n+-type source regions 5. A drain electrode 8 is formed on a bottom surface of the n-type semiconductor substrate 1.
FIG. 2A is a fragmentary plane view illustrative of a first conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate. FIG. 2B is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the first conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-Axe2x80x2 line of FIG. 2A
With reference to FIG. 2A, a plurality of square-shaped double diffused MOS field effect transistor cells are aligned in matrix, wherein the shape of each of the square-shaped double diffused MOS field effect transistor cells is defined by a boundary line between outside edges of the source region 5 and channel regions 14. Each of the square-shaped double diffused MOS field effect transistor cells is surrounded by a square-frame shaped channel region 14. A square-shaped boundary broken line 9 corresponds to the outside edge of the square-frame shaped channel region 14 or the outside edge of the base region 4. Adjacent two of the square-shaped double diffused MOS field effect transistor cells are distanced from each other.
With reference to FIG. 2B, the p-type base regions 4 are selectively formed in selected upper regions of the n-type semiconductor substrate 1. The n+-type source regions 5 are selectively formed in selected upper regions of the p-type base regions 4. Each of the square-frame shaped channel regions 14 is defined between the outside edges of the n+-type source regions 5 and the outside edge of the p-type base region 4. The gate oxide film 2 is selectively formed on the n-type semiconductor substrate 1 and on the square-frame shaped channel regions 14. The phosphorus doped polysilicon gate electrode 3 is provided on the gate oxide film 2. The inter-layer insulator 6 is provided, which covers the phosphorus doped polysilicon gate electrode 3 and the outside half regions of the n+-type source regions 5. The aluminum electrode layer 7 is provided which entirely extends over the inter-layer insulator 6 and inside half regions of the n+-type source regions 5. The drain electrode 8 is provided on the bottom surface of the n-type semiconductor substrate 1.
FIG. 3A is a fragmentary plane view illustrative of a second conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate. FIG. 3B is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the second conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-Axe2x80x2 line of FIG. 3A.
With reference to FIG. 3A, a plurality of circular-shaped double diffused MOS field effect transistor cells are aligned in two dimensional staggered alignment, wherein the shape of each of the circular-shaped double diffused MOS field effect transistor cells is defined by a boundary circular line between outside edges of the annular-shaped source region 5 and circular-frame shaped channel regions 14. Each of the circular-shaped double diffused MOS field effect transistor cells is surrounded by the circular-frame shaped channel region 14. A circular-shaped boundary broken line 9 corresponds to the outside edge of the circular-frame shaped channel region 14 or the outside edge of the base region 4. Adjacent two of the circular-shaped double diffused MOS field effect transistor cells are distanced from each other.
With reference to FIG. 3B, the p-type base regions 4 are selectively formed in selected upper regions of the n-type semiconductor substrate 1. The n+-type source regions 5 are selectively formed in selected upper regions of the p-type base regions 4. Each of the circular-frame shaped channel regions 14 is defined between the outside edges of the n+-type source regions 5 and the outside edge of the p-type base region 4. The gate oxide film 2 is selectively formed on the n-type semiconductor substrate 1 and on the circular-frame shaped channel regions 14. The phosphorus doped polysilicon gate electrode 3 is provided on the gate oxide film 2. The inter-layer insulator 6 is provided, which covers the phosphorus doped polysilicon gate electrode 3 and the outside half regions of the n+-type source regions 5. The aluminum electrode layer 7 is provided which entirely extends over the inter-layer insulator 6 and inside half regions of the n+-type source regions 5. The drain electrode 8 is provided on the bottom surface of the n-type semiconductor substrate 1.
FIG. 4A is a fragmentary plane view illustrative of a third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate. FIG. 4B is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-Axe2x80x2 line of FIG. 4A. FIG. 4C is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along a B-Bxe2x80x2 line of FIG. 4A.
With reference to FIG. 4A, a plurality of modified band shaped double diffused MOS field effect transistor cells extend in parallel to each other in a diagonal direction, wherein each of the modified band shaped double diffused MOS field effect transistor cells comprises a plurality of square-shaped expanding portions which are distanced from each other at a constant pitch and diagonally extending straight band portions connecting the adjacent two of the square-shaped expanding portions. The square-shaped expanding portions of the modified band shaped double diffused MOS field effect transistor cells are aligned in matrix. In view of the diagonal direction along the diagonally extending straight band portions of the modified band shaped double diffused MOS field effect transistor cells, however, the square-shaped expanding portions of the modified band shaped double diffused MOS field effect transistor cells show a staggered alignment. The shape of each of the modified band shaped double diffused MOS field effect transistor cells is defined by boundary lines between outside edges of the source region 5 and channel regions 14. Each of the modified band shaped double diffused MOS field effect transistor cells is surrounded by a modified-line shaped channel region 14. A modified-line boundary broken line 9 corresponds to the outside edge of the modified-line shaped channel region 14 or the outside edge of the base region 4. Adjacent two of the modified band shaped double diffused MOS field effect transistor cells are distanced from each other in another diagonal direction vertical to the above diagonal direction along which the modified band shaped double diffused MOS field effect transistor cells extend.
With reference to FIG. 4B, the p-type base region 4 is selectively formed in a selected upper region of the n-type semiconductor substrate 1. The n+-type source regions 5 are selectively formed in selected upper regions of the p-type base regions 4. Each of the square-fame shaped channel regions 14 is defined between the outside edges of the n+-type source regions 5 and the outside edge of the p-type base region 4. The gate oxide film 2 is selectively formed on the n-type semiconductor substrate 1 and on the square-frame shaped channel regions 14. The phosphorus doped polysilicon gate electrode 3 is provided on the gate oxide film 2. The inter-layer insulator 6 is provided, which covers the phosphorus doped polysilicon gate electrode 3 and the outside half regions of the n+-type source regions 5. The aluminum electrode layer 7 is provided which entirely extends over the inter-layer insulator 6 and inside half regions of the n+-type source regions 5. The drain electrode 8 is provided on the bottom surface of the n-type semiconductor substrate 1.
With reference to FIG. 4C, the p-type base region 4 is selectively formed in a selected upper region of the n-type semiconductor substrate 1. The n+-type source region 5 is selectively formed in selected upper regions of the p-type base regions 4. Each of the square-frame shaped channel regions 14 is defined between the outside edges of the n+-type source region 5 and the outside edge of the p-type base region 4. The gate oxide film 2 is selectively formed on the n-type semiconductor substrate 1 and on the square-frame shaped channel regions 14. The phosphorus doped polysilicon gate electrode 3 is provided on the gate oxide film 2. The inter-layer insulator 6 is provided, which covers the phosphorus doped polysilicon gate electrode 3 and the outside half regions of the n+-type source region 5. The aluminum electrode layer 7 is provided which entirely extends over the inter-layer insulator 6 and an inside half region of the n+-type source region 5. The drain electrode 8 is provided on the bottom surface of the n-type semiconductor substrate 1.
The most important properties of the double diffused MOS field effect transistor are a possible reduced ON-resistance, a possible reduced threshold voltage and a possible increased source-drain withstand voltage. The ON-resistance is given by the sum of a channel resistance and a bulk resistance. FIG. 5 is a diagram illustrative of variations in ratio of a channel resistance to an ON-resistance over a source-drain withstand voltage of the double diffused MOS field effect transistor. The ratio of the channel resistance to the ON-resistance is simply decreased by increasing the source-drain withstand voltage of the double diffused MOS field effect transistor. In the low channel resistance region, the channel resistance is more dominative than the bulk resistance. In the low channel resistance region, therefore, it is more important how to reduce the channel resistance as many as possible in order to reduce the ON-resistance. The channel resistance of the double diffused MOS field effect transistor is given by the following equation.                     Rch        =                  1          /                      {                                          (                                  W                  /                  L                                )                            ⁢                              C                0                            ⁢                              μ                ⁡                                  (                                                            V                      GS                                        -                                          V                      th                                                        )                                                      }                                                  =                  a          /          W                                        =                  1          /                      {                          b              ⁡                              (                                                      V                    GS                                    -                                      V                    th                                                  )                                      }                              
where Rch is the channel resistance of the double diffused MOS field effect transistor, W is the channel width of the channel region, L is the channel length of the channel region, C0 is the capacity of the gate oxide film, xcexc is the majority carrier mobility, VGS is the gate-source voltage, Vth is the threshold voltage, and xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are constants.
The above equation shows that the channel resistance of the double diffused MOS field effect transistor is inversely proportional to the channel width of the channel region. This means that in order to reduce the channel resistance, it is required to increase the channel width.
The above equation also shows that the channel resistance of the double diffused MOS field effect transistor is decreased by decreasing the threshold voltage of the double diffused MOS field effect transistor. This means that in order to reduce the channel resistance, it is required to decrease the threshold voltage of the double diffused MOS field effect transistor.
The threshold voltage of the double diffused MOS field effect transistor is further given by the following equation.                     Vth        =                  xe2x80x83                ⁢                              V            FB                    +                      2            ⁢            φ            ⁢                          xe2x80x83                        ⁢                          F              P                                +                                    {                              2                ⁢                Ks                ⁢                                  xe2x80x83                                ⁢                                  ϵ                  0                                ⁢                                                      qN                    A                                    ⁡                                      (                                          2                      ⁢                      φ                      ⁢                                              xe2x80x83                                            ⁢                                              F                        P                                                              )                                                              }                                                              =                  xe2x80x83                ⁢                              (                                          N                A                                      )                    /          C                    
where Vth is the threshold voltage of the double diffused MOS field effect transistor, VFB is the flat band potential, xcfx86 is the electrostatic potential, FP is the flux of holes, KS is the dielectric constant of silicon, xcex50 the dielectric constant in vacuum, q is the charge of electron, NA is the acceptor or donor concentration of the channel region, and xe2x80x9ccxe2x80x9d is the constant.
The above equation shows that the threshold voltage of the double diffused MOS field effect transistor is decreased by decreasing the acceptor or donor concentration of the channel region. Since the channel regions are formed in the base region, the acceptor or donor concentration of the channel region is equal to the acceptor or donor concentration of the base region.
Consequently, the decrease in the acceptor or donor concentration of the base region results in the decreases in threshold voltage and ON-resistance of the double diffused MOS field effect transistor. The increase in the acceptor or donor concentration of the base region results in the increases in threshold voltage and ON-resistance of the double diffused MOS field effect transistor. In order to realize possible reductions in threshold voltage and ON-resistance of the double diffused MOS field effect transistor, it is required to reduce the acceptor or donor concentration of the base region. Notwithstanding, an excessive reduction in the acceptor or donor concentration of the base region makes a space charge region easy to expend in the base region so that a punch through phenomenon may be caused, thereby dropping the source-drain withstand voltage.
The above first to third conventional two-dimensional arrays of the plurality of double diffused MOS field effect transistors are engaged with the following problems.
The first conventional two-dimensional array of a plurality of double diffused MOS field effect transistors illustrated in FIG. 2A has the following disadvantages. The square-shaped double diffused MOS field effect transistor cells are aligned in matrix so that adjacent two of the square-shaped double diffused MOS field effect transistor cells are distanced from each other, for which reason a density of the square-shaped double diffused MOS field effect transistor cells is low. This low density of the square-shaped double diffused MOS field effect transistor cells means that it is difficult to increase a total width of the channel widths of the channel regions in a unit area of the semiconductor substrate. FIG. 6 is a partial enlarged plane view illustrative of a corner of the square-shaped double diffused MOS field effect transistor cell, where the acceptor concentration of the p-type base region in the vicinity of the corner of the square-shaped double diffused MOS field effect transistor cell is lower than the other portions of the p-type base region. The lower acceptor concentration of the p-type base region in the vicinity of the corner of the square-shaped double diffused MOS field effect transistor cell makes the punch through phenomenon likely to appear, whereby the source-drain withstand voltage is dropped. Even if the acceptor concentration of the base region is increased in order to prevent the drop of the source-drain withstand voltage or appearance of the punch through phenomenon, then the increase in the acceptor concentration of the base region makes it difficult to reduce the threshold voltage, whereby the difficulty in reduction of the threshold voltage makes it difficult to reduce the ON-resistance of the double diffused MOS field effect transistor.
The second conventional two-dimensional array of a plurality of double diffused MOS field effect transistors illustrated in FIG. 3A has the following disadvantages. The circular-shaped double diffused MOS field effect transistor cells are aligned in two-dimensional staggered alignment, so that adjacent two of the circular-shaped double diffused MOS field effect transistor cells are distanced from each other. Notwithstanding, the two-dimensional staggered alignment may increase the density of the circular-shaped double diffused MOS field effect transistor cells. However, the circular-shape of the circular-shaped double diffused MOS field effect transistor cells shortens a individual channel width of each of the circular-shaped double diffused MOS field effect transistor cells as compared to the square-shape of the square-shaped double diffused MOS field effect transistor cells. This circular-shape of the circular-shaped double diffused MOS field effect transistor cells makes it difficult to increase a total width of the channel widths of the channel regions in a unit area of the semiconductor substrate. The difficulty in increase in the total width of the channel widths of the channel regions of the circular-shaped double diffused MOS field effect transistors makes it difficult to reduce the channel resistance of the circular-shaped double diffused MOS field effect transistors. The difficulty in reduction of the channel resistance of the circular-shaped double diffused MOS field effect transistors means it difficult to reduce the ON-resistance of the double diffused MOS field effect transistor.
The third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors illustrated in FIG. 4A has the following disadvantages. The modified band shaped double diffused MOS field effect transistor cells are aligned in parallel to each other so that adjacent two of the modified band shaped double diffused MOS field effect transistor cells are distanced from each other, for which reason a density of the modified band shaped double diffused MOS field effect transistor cells is low. However, each of the modified band shaped double diffused MOS field effect transistor cells has wide channel width. This makes it easy to increase the total width of the channel regions of the modified band shaped double diffused MOS field effect transistor cells. Notwithstanding, each of the modified band shaped double diffused MOS field effect transistor cells comprises a plurality of the square-shaped expanding portions which are distanced from each other at a constant pitch and the diagonally extending straight band portions connecting the adjacent two of the square-shaped expanding portions. Namely, each of the square-shaped expanding portions of each of the modified band shaped double diffused MOS field effect transistor cells has two corners, where the acceptor concentration of the p-type base region in the vicinity of the corner of the square-shaped expanding portions of the modified band shaped double diffused MOS field effect transistor cell is lower than the other portions of the p-type base region. The lower acceptor concentration of the p-type base region in the vicinity of the corner of the square-shaped expanding portions of the modified band shaped double diffused MOS field effect transistor cell makes the punch through phenomenon likely to appear, whereby the source-drain withstand voltage is dropped. Even if the acceptor concentration of the base region is increased in order to prevent the drop of the source-drain withstand voltage or appearance of the punch through phenomenon, then the increase in the acceptor concentration of the base region makes it difficult to reduce the threshold voltage, whereby the difficulty in reduction of the threshold voltage makes it difficult to reduce the ON-resistance of the double diffused MOS field effect transistor. The above third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors illustrated in FIG. 4A has a further disadvantage as follows. FIG. 7A is a schematic view illustrative of a parasitic transistor as formed at a center portion of the square-shaped expanding portion of the modified band shaped double diffused MOS field effect transistor cell in FIG. 4B. In order to inactivate the parasitic bipolar transistor, a short circuit is formed between the source region 5 and the base region 4. FIG. 7B is a schematic view illustrative of a parasitic transistor as formed at a center portion of the diagonally extending straight band portion of the modified band shaped double diffused MOS field effect transistor cell in FIG. 4C. Since the diagonally extending straight band portion of the modified band shaped double diffused MOS field effect transistor cell is slender, it is difficult to form any short circuit between the source region 5 and the base region 4, for which reason the parasitic bipolar transistor is allowed to be activated.
In the above circumstances, it had been required to develop a novel two-dimensional array of the double diffused MOS field effect transistor cells free from the above problems and disadvantages.
Accordingly, it is an object of the present invention to provide a novel semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells having a reduced ON-resistance between source and drain.
It is a still further object of the present invention to provide a novel semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells having a reduced threshold voltage.
It is yet a further object of the present invention to provide a novel semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells having an increased source-drain withstand voltage.
It is a further more object of the present invention to provide a novel semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells free from any parasitic transistor.
The first present invention provides a semiconductor device having a plurality of double diffused field effect transistor cells so aligned in two-dimension that each of at least a majority of the double diffused field effect transistor cells has plural sides bounded with plural channel regions and plural corners free of any bound with the plural channel regions. The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.